Exemplary embodiments relate to a semiconductor device and an operating method thereof and, more particularly, to a detrap method in a program operation.
A semiconductor device includes a plurality of memory cells for storing data. To store data in the memory cells, a program operation is performed. In the program operation, some electrons may be trapped in a specific layer, and the trapped electrons are capable of deteriorating an electrical characteristic of the memory cells. This electron trapping phenomenon is described below with reference to FIG. 1.
FIG. 1 is a cross-sectional view of a memory cell illustrating the features of a conventional program operation.
Referring to FIG. 1, the memory cell includes a tunnel insulating layer 13, a charge trap layer 14, a dielectric layer 15, and a control gate 16 sequentially stacked over a semiconductor substrate 11. Junctions 12 are formed in the semiconductor substrate 11 on both sides of the memory cell. The junctions 12 are formed within a well formed in the semiconductor substrate 11, and the tunnel insulating layer 13 and the well partially overlap with each other. The charge trap layer 14 is also called a floating gate. The control gate 16 is coupled to a word line WL. The tunnel insulating layer 13 is formed of an oxide layer. The charge trap layer 14 and the control gate 16 are formed of conductive layers (for example, polysilicon layers). The dielectric layer 15 has a stack structure including a high dielectric layer (or an oxide layer), a nitride layer, and an oxide layer.
A program operation on the memory cells is performed by supplying a program voltage to the word line WL when a program permission voltage (for example, 0 V) is supplied to the well and bit lines. When the high program voltage is supplied to the word line WL, some of electrons in the well move to the charge trap layer 14 via the tunnel insulating layer 13 by means of Fowler-Nordheim (FN) tunneling. The programmed memory cells have different threshold voltages according to the amount of electrons trapped in the charge trap layer 14. When the threshold voltage of a specific memory cell reaches a target level, the memory cell corresponds to a programmed cell. When the threshold voltage of the memory cell is lower than the target level, the memory cell corresponds to a non-programmed (or erase) cell.
A read operation on memory cells is performed by supplying a read voltage to a word line WL coupled to the memory cells. The state of the memory cell may be determined according to whether the threshold voltage of the memory cell is higher or lower than the read voltage.
As described above, the data of the memory cells is determined by the threshold voltages of the memory cells, and the threshold voltage of the memory cell is determined by the number of electrons trapped in the charge trap layer 14 (more specifically, the number of programmed electrons).
In a program operation, however, some electrons may be trapped in the tunnel insulating layer 13 without passing into the charge trap layer 14. The threshold voltage of the memory cell may be shifted by the electrons trapped in the tunnel insulating layer 13. In particular, an electrical characteristic of the tunnel insulating layer 13 is gradually deteriorated as program, erase, and read operations are repeatedly performed. Accordingly, the number of electrons trapped in the tunnel insulating layer 13 may be increased according to an increase in the number of operations on the semiconductor device.